1. Field of the Invention
The present invention relates to a motor driving circuit, and more particularly, to a motor driving circuit having low current consumption under a standby mode.
2. Description of the Prior Art
A conventional DC motor is equipped with a specific driving circuit, for manipulating a driving voltage of the DC motor or occasions for operating the DC motor. The conventional DC motor is primarily operated by magnetic forces, which are generated from repeated variation of electromagnetic forces generated by two torques, where both the torques are inverse in orientations and are generated by magnetic fields, which are generated by repeatedly changed orientations of currents, in the DC motor. However, under certain circumstances, the conventional DC motor is not required to operate, and therefore, power of the DC motor has to be reduced at this time for avoiding unnecessary power consumption.
FIG. 1 is a diagram of a conventional DC motor driving circuit 100. As shown in FIG. 1, the DC motor driving circuit 100 includes a driving module 101. The driving module 101 includes a control module 102, an H-shaped full-bridge circuit 104, an operational amplifier 106, a comparator 108, a transistor 110, a lock/restart module 112, and a thermal shutdown module 114. The DC motor driving circuit 100 further comprises a motor 116, a frequency generating resistor 118, a motor driving voltage source 120, a first diode 122, a capacitor 124, a Hall sensor 126, and a conventional resistor 128. The H-shaped full-bridge circuit 104 has a first input terminal coupled to a first output terminal of the control module 102, a second input terminal coupled to a second output terminal of the control module 102, a third input terminal coupled to a third output terminal of the control module 102, and a fourth input terminal coupled to a fourth output terminal of the control module 102. The H-shaped full-bridge circuit 104 has a first output terminal coupled to a pin OUT1 of the driving module 101, and a second output terminal coupled to a pin OUT2 of the driving module 101. The operational amplifier 106 has a first output terminal coupled to a first input terminal of the control module 102, a second output terminal coupled to a second input terminal of the control module 102, a first input terminal coupled to a pin H+ of the driving module 101, and a second input terminal coupled to the pin H− of the driving module 101. The comparator 108 has a first input terminal coupled to the first input terminal of the control module 102, and a second input terminal coupled to the second input terminal of the control module 102. The transistor 110 has a gate coupled to a first output terminal of the comparator 108, a source coupled to ground, and a drain coupled to a pin FG of the driving module 101. The lock/restart module 112 has an input terminal coupled to the second output terminal of the comparator 108, and an output terminal coupled to a third input terminal of the control module 102. The thermal shutdown module 114 has an output terminal coupled to a fourth input terminal of the control module 102. The motor 116 has a first terminal coupled to the pin OUT1 of the driving module 101, and a second terminal coupled to the pin OUT2 of the driving module 101. The frequency generating resistor 118 has a first terminal coupled to the pin FG of the driving module 101. The motor driving voltage source 120 has a positive terminal coupled to a second terminal of the frequency generating resistor 118, and a negative terminal coupled to ground. The first diode 122 has a positive bias terminal coupled to the positive terminal of the motor driving voltage source 120. The capacitor 124 has a first terminal coupled to both the negative terminal of the motor driving voltage source 120 and a pin VDD of the driving module 101, and a second terminal coupled to ground. The Hall sensor 126 has a first output terminal coupled to the pin H+ of the driving module 101, a second output terminal coupled to the pin H− of the driving module 101, and a negative bias terminal coupled to ground. The resistor 128 has a first terminal coupled to a positive bias terminal of the Hall sensor 126, and a second terminal coupled to the pin VDD.
The H-shaped full-bridge circuit 104 includes four transistors as shown in FIG. 1, where the four transistors include a first P-type MOSFET 130, a second P-type MOSFET 134, a first N-type MOSFET 138, and a second N-type MOSFET 142. The H-shaped full-bridge circuit 104 further includes four diodes as shown in FIG. 1, where the four diodes include a second diode 132, a third diode 134, a fourth diode 140, and a fifth diode 144. The first P-type MOSFET 130 has a gate coupled to the first input terminal of the H-shaped full-bridge circuit 104. The second diode 132 has a first terminal coupled to a drain of the first P-type MOSFET 130, and a second terminal coupled to a source of the first P-type MOSFET 130. The second P-type MOSFET 134 has a gate coupled to the third input terminal of the H-shaped full-bridge circuit 104. The third diode 136 has a first terminal coupled to a drain of the second P-type MOSFET 134, and a second terminal coupled to a source of the second P-type MOSFET 134. The first N-type MOSFET 138 has a gate coupled to the second input terminal of the H-shaped full-bridge circuit 104, and a drain coupled to the drain of the first P-type MOSFET 130. The fourth diode 140 has a first terminal coupled to a source of the first N-type MOSFET 138, and a second terminal coupled to the drain of the first N-type MOSFET 138. The second N-type MOSFET 142 has a gate coupled to the fourth input terminal of the H-shaped full-bridge circuit 104, and a drain coupled to the drain of the second P-type MOSFET 134, and a source coupled to the source of the first N-type MOSFET 134. The fifth diode 144 has a first terminal coupled to the source of the second N-type MOSFET 142, and a second terminal coupled to the drain of the second N-type MOSFET 142. Note that both the sources of the first P-type MOSFET 130 and the second P-type MOSFET 134 are coupled to the pin VDD for receiving a voltage inputted at the pin VDD. Both the sources of the first N-type MOSFET 138 and the second N-type MOSFET 142 are coupled to ground. All of the first P-type MOSFET 130, the second P-type MOSFET 134, the first N-type MOSFET 138, and the second N-type MOSFET 142 are utilized for providing required currents for driving the motor 116.
The DC motor driving circuit 100 is biased with both a DC voltage, which is inputted through the pin VDD, and ground, which is coupled through the pin GND. The control module 102 is utilized for controlling voltage levels of gates of the first P-type MOSFET 130, the second P-type MOSFET 134, the first N-type MOSFET 138, and the second N-type MOSFET 142, for switching on or switching off the listed MOSFETs, and for tuning a required current for driving the motor 116. The control module 102 may be implemented with a digital logic circuit or an analog amplifier control circuit. Bias voltages of the Hall sensor 126 are determined by both the voltage level at the pin VDD and the resistance of the resistor 128. The operational amplifier 106 is utilized for amplifying voltage levels, which are outputted from the Hall sensor 126 and at the pins H+ and H− , so that the amplified voltage levels are respectively outputted at nodes PO and NO, as shown in FIG. 1, for usage of succeeding elements. The lock/restart module 112 transmits a command for ordering the control module 102 to shut down transistors of the H-shaped full-bridge circuit 104 when fans of the motor 116 are jammed. After the transistors of the H-shaped full-bridge circuit 104 are shut down for a while, the lock/restart module 112 transmits another command to the control module 102 for activating the motor 116 by turning on the transistors. The comparator 108 is utilized for switching on or switching off the transistor 110. When the transistor 110 is switched on by receiving an output signal from the first output terminal of the comparator 108, the voltage level at the drain of the transistor 110, i.e., the voltage level at the pin FG, may be detected from an external system, where the signal at the pin FG indicates a rotational velocity of the motor 116. Moreover, when an output signal is outputted from the first output terminal of the comparator 108, a reset signal is also outputted from the second output terminal of the comparator 108 to the lock/restart module 112 for resetting the status of the lock/restart module 112, where the reset signal is a one shot pulse. The thermal shutdown module 114 is utilized for ordering the control module 102 to shut down the transistors of the H-shaped full-bridge circuit 104 when the motor 116 is overheated. Therefore, the H-shaped full-bridge circuit 104 ceases generating biasing currents, and the temperature of the motor 116 ceases increasing as well. The motor driving voltage source 120 is utilized for providing required bias voltages of the H-shaped full-bridge circuit 104 (or the DC motor driving circuit 100 as well) through the pin VDD. The first diode 122 is utilized for preventing currents from the pin VDD from reversely flowing to the motor driving voltage source 120 with its reverse bias. Besides, when the motor driving voltage source 120 is erroneously connected in poles, the first diode 122 prevents the DC motor driving circuit 100 from being burnt down as well. The capacitor 124 is utilized for draining backflow currents of the motor 116, and for stabilizing the voltage level at the pin VDD. The Hall sensor 126 is utilized for detecting the magnetic filed generated by operations of the motor 116 to output corresponding signals to both the pins H+ and H− so that the DC motor driving circuit 100 is informed with variations of the magnitude of the magnetic field. Note that the motor 116 indicates an inductive loading so as to store electric power. The pin PWM receives pulse width modulation (PWM) signals from a system terminal, where switching on or switching off the transistors of the H-shaped full-bridge circuit 104 by the control module 102 primarily follows the pulse width modulation signals when the motor 116 is normally operated. For example, when the motor 116 is normally operated, and when the pulse width modulation signal stays high, the transistors of the H-shaped full-bridge circuit 104 switches on or switches off by following voltage levels of both the pins H+ and H−, and the motor 116 is biased by the voltage level at the pin VDD. When the motor 116 is normally operated, and when the pulse width modulation signal stays low, both the first P-type MOSFET 130 and the second P-type MOSFET 134 are switched off, and both the first N-type MOSFET 138 and the second N-type MOSFET 142 are switched on. At this time, the voltage level at the pin VDD is isolated by both the shut-down transistors, and the motor 116 cannot be biased with the pin VDD so that power consumption is saved.
Please refer to FIG. 2, which is a waveform diagram of voltage levels at pins of the DC motor driving circuit 100 shown in FIG. 1 when the control module 102 shown in FIG. 1 is implemented with an analog amplifier controlling circuit. Note that the symbol “Imotor” shown in FIG. 2 indicates a bias current of the motor 116. As shown in FIG. 2, at the moment when the voltage levels at both the pins H+ and H− intersect, i.e., when the magnetic pole of the motor 116 is changed, envelopes of the voltage levels at both the pins OUT1 and OUT2 vary smoothly between a positive voltage level and a negative voltage level, and therefore, the current Imotor varies smoothly so that less noises from the motor 116 are generated. However, when the control module 102 is implemented with a digital logic circuit, the envelopes of the voltage levels at both the pins OUT1 and OUT2 vary significantly between the high voltage level and the low voltage level, and therefore, the current Imotor vary sharply so that more noises from the motor 116 are generated. But the power consumption of the motor 116 is smaller when the control module 102 is implemented with the digital logic circuit. Note that the analog amplifier controlling circuit is merely an exemplary embodiment of the control module 102 in voltage level transition, and other conventional embodiments are not further described herein. Note that the frequency of the signal at the pin FG is the same with the signals at both the pins H+ and H−, and therefore, the frequency of the signal at the pin FG is able to indicate a rotational frequency of the motor 116 so that the system terminal may be informed with a corresponding rotational velocity of the motor 116. At last, the system terminal accordingly outputs a pulse width modulation signal having an adequate duty cycle for ordering the control module 102 to tune the rotational velocity of the motor 116. When the system terminal is overheated, the duty cycle of the pulse width modulation signal is increased for increasing both the bias current and the rotational velocity of the motor 116 to enhance heat dissipation of the system terminal. When the temperature of the system terminal is decreased so that the motor 116 is not required to enhance heat dissipation, the system terminal accordingly outputs a pulse width modulation signal having a smaller duty cycle (even 0%) for reducing the bias current of the motor 116, and for saving unnecessary power consumption of the motor 116 as well.
Please refer to FIG. 3, which is a waveform diagram of voltage levels at certain pins illustrated in FIG. 2 when the motor 116 shown in FIG. 1 is locked by unknown reasons. As shown in FIG. 3, in the operating period, voltage levels at the pins H+, H−, OUT1, OUT2, and FG are normal when the motor 116 are normally operated. However, in the first restart period, since fans of the motor 116 are jammed or interrupted magnetically, voltage levels at the pins H+ and H− are kept constant. The voltages levels at the pins OUT1 and OUT2 for indicating a voltage difference of the motor 116 are kept constant as well so that there are no changes in the magnetic field, but the voltage level at the pin OUT1 stays high for keeping on restarting the motor 116. At this time, since the motor 116 is not operated, the voltage level at the pin FG for indicating a rotational frequency of the motor 116 stays at low. After the first restart period is over, since there are no responses in the motor 116 for a while, for saving power consumption, the voltage level at the pin OUT1 is changed to be low for significantly weakening the current flowing through the motor 116 during the standby periods shown in FIG. 3. After several successive restart periods along with several standby periods pass, when the factor for hindering the motor 116 from operating is removed in a certain restart period or a certain standby period, the restart/operating period shown in FIG. 3 begins, and the motor 116 may be normally operated again by the voltage difference between the pins OUT1 and OUT2. Moreover, voltage levels at other pins shown in FIG. 3 are back to normal as well.